Welcome to Redwood EDA

for the next age of silicon

WE BELIEVE IN

A FUTURE...

...where open-source silicon shapes the industry.

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Open-Source Si

Our tools are free online for open-source silicon development. We are active on GitHub, providing flexible components and RISC-V IP.

…where AI frees designers to focus on what designers do best.

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AI Assistance

For AI and humans to work as a team, hardware must be modeled to facilitate safe and understandable manipulation. This is TL-Verilog.

…where every challenge is met with bespoke silicon.

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Optimal means custom. EDA must enable an individual to implement an ASIC, not a team of a hundred.

Bespoke Si

Since the introduction of RTL...

...silicon integration has scaled 400,000x !

RTL was not built for this.

Transaction-level design methodology was conceived for the next 400,000x.

We help organizations to enable and benefit from Transaction-Level Verilog.

And will NOT:

Break anything you do today
Delay your next milestone

Which can:

Accelerate development
Increase resilience
Enable reuse
Improve silicon quality
Save money

BENEFITS

EVERYONE

(Tap to see how.)

ACADEMIA

Manager

Physical Designer

Architect

Post Si Engineer

USERS

Verification Engineer

INDUSTRY

Hobbyist

Startup Founder

I empowered my team to “shift-left” without skipping a beat. We share IP more easily, bring new models up faster, and expose issues sooner. When project goals change, we’re able to adjust.

With RTL simple timing fixes require help from my logic designer to implement, test, and integrate the change. Sometimes verification models even break. With TL-Verilog I often make fixes on my own without the fear of breaking the model.

DFx requires every logic designer to do their part. It is often an afterthought that gets dropped. With TL-Verilog a single logic designer can stitch DFx logic throughout the model in isolated code, avoiding confusion and late churn. In addition, higher-level modeling improves silicon health.

I can do more than make slides. My early architectural and performance models serve as documentation and evolve into RTL.

Using TL-Verilog, I code new logic the way I think about it -- as state, pipelines, and transactions. Since I don't need to maintain staging flops, clock gating, and signal stitching manually, I can easily adjust my RTL IP for different customers.

I am able to attach my transactors, checkers, assertions, and cover statements to TL-Verilog DUTs at a higher level of abstraction, so they are less affected by changes. And TL-Verilog is great for synthesizable verification modeling.

Using makerchip.com, students are coding circuits on day one. I cover digital logic and computer architecture in a single class, and I provide remote learning with a virtual lab experience using the 1st CLaaS framework for cloud FPGAs.

Redwood EDA made it possible for me to developed open-source silicon for free online and deploy to cloud FPGAs. Now individuals like me can play a part in this industry.

TL-Verilog significantly lowers the barrier to entry for hardware modeling and cloud FPGA development, so, on a small scale, I can introduce new innovations that compete with bigger players in the industry.

Learning TL-Verilog was easy and fun. I was able to design and implement a complete RISC-V CPU from scratch. In interviews, it helped me stand out and land a job with an innovative company where I can make a difference.

Not only does TL-Verilog accelerate our existing uarch research, it also elevates EDA to a higher plane, opening the door to a new world of research opportunities.