For Architects

 

High-Level Modeling (HLM): Yes, we know, you are really good with PowerPoint® and maybe even Visio®, but do you remember the days when you actually created real code that did something? We're giving you back your modeling power.  High-Level Models in TL-Verilog are four to eight times smaller than they would be in SystemVerilog, and, unlike PowerPoint® slides, you can actually do something with them, and so can others.  It's hard to find a bug in a PowerPoint® slide, but simulation doesn't lie.

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Top-Down Design: Your HLM can live on.  Provide the logic team with a starting point.  They will thank you for it, and they will be less likely to reinvent your architectural vision.  A TL-Verilog HLM can be evolved into production RTL, and it won't lose all of its high-level design intent.

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Performance Modeling: High-Level TL-Verilog models can be used for performance modeling.  While simulation may be a bit slower than other modeling methods, simulation is not the only option.  Since TL-Verilog is synthesizable, hardware emulation becomes possible for dramatic speedups.

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Early Verification: It enables the verification team to begin their work earlier, and verification is always the long pole to tape-out.  An early verification environment keeps the logic work on track.

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Early Physical Feedback: Sure, your TL-Verilog HLM is not yet implementable, but it is analyzable.  The physical team can get to work on major array structures and provide feasibility feedback.