For Logic Designers

 

Work Smarter: SandPiper takes the tedium out of logic design.  Half the code to do the same job -- you can enjoy your work and spend your evenings with your family.  SystemVerilog is a language for creating event-based simulators that model hardware behavior.  TL-Verilog lets you directly model the hardware, leaving simulation details to the tools.  Pipeline and transaction constructs directly capture design intent.

​

"The connection between the language in which we think/program and the problems and solutions we can imagine is very close."

-- B. Stroustrup (creator of C++)​​​​​​​​​

​​​​​​

 

 

 

 

 

 

 

 

Break the Tug-of-War: Verification on one side and implementation on the other, and you are the rope pulled in both directions, unable to satisfy either side.  The verification team wants simple abstract interfaces, and the implementation team needs interfaces to be physically-optimized.  The verification team wants stability and new functionality, while the physical team needs disruptive changes to close timing.  And it takes time to get even a simple change through regression testing.  SandPiper will help you make them both happy.  TL-Verilog enables logic retiming that is safe for the physical team to make independently without any risk of breaking functionality or breaking verification collateral. They can make progress without you, freeing up your focus for new functionality.

​

It Won't Hurt: SandPiper adds capabilities without giving anything up:

• TL-Verilog is a language extension, so nothing is taken away.

• SandPiper typically runs in a fraction of a second, so it adds little to your build time.  In fact, it generally saves you build time by acting as a fast filter for syntax errors.  (Also, in this manner, it saves on license usage and costs of other tools.)

• Generally, with generated code, it is difficult to correlate errors back to the source code.  Not so with SandPiper.  Generated code is generally either correct-by-construction or it is translated line-for-line from the source code, so an error on line 147 is an error on line 147. If you use multiline text macros, this may no longer be the case, but in Makerchip and SandStorm, a button click will take you to the source line.