For Physical Designers

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Be Empowered: Tired of waiting for the logic team to make the necessary RTL changes?  Encourage your logic designers to use TL-Verilog, so you can take control.  Many of the changes necessary to meet timing can be made by you safely without the need for regression testing, without any help from your logic designers.  Try the first few tutorials in the Makerchip IDE to get the idea or read this paper on Timing Abstraction.​​