For Professors

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TL-Verilog is ideal for education: You want to use SystemVerilog to teach logic and microarchitecture, but learning SystemVerilog requires three big books and a big reference manual.  You can take your whole semester and cover a fraction of it.  TL-Verilog greatly simplifies things.  It introduces new constructs that correspond to the microarchitecture concepts you need to teach -- state, pipelines, and transactions.  All the language overhead that exists for describing event-based simulation models is not required, so you can focus on logic and microarchitecture.  With code that's half the size, you can give assignments that are actually meaningful.

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Online assignments: Makerchip.com is a perfect environment for class assignments in TL-Verilog.

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Skills for the future: Teach the skills of tomorrow, not the skills of today.  Put your students ahead of the curve.

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Help is available: We are interested in co-developing curricula.  Let us know your interest, and let's see what we can do together.