For Verification Engineers

 

Visualization: "Visual Debug" is generally the starting point with SandPiper and SandStorm. SandPiper provides huge benefits to verification if your logic designers use TL-Verilog, but that may not be up to you. Visual Debug, however, works with pure Verilog and even other HDLs. A small investment in developing visualizations can improve communication and understanding of the model, improve the debugging experience, and provide a form of documentation you can trust. It's a great task for interns and junior engineers that benefits the whole team.

 

Verification Modeling: TL-Verilog is designed for modeling synchronous digital behavior, be it hardware or verification models like transactors and reference models.  Even if hardware modeling is in Verilog, TL-Verilog can provide the gasket for transaction-level and timing-abstract verification models.

 

Hardware Emulation: TL-Verilog provides synthesizable constructs for Transaction-Level Modeling.  Your TL-Verilog transactors, reference models, and assertions can be synthesized for hardware emulation rather than running them as software.  You can get top speeds without disabling checking, and no gaskets are required between verification models on the hosts and synthesized hardware logic.

 

You want your logic designers to use TL-Verilog:

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Earlier Models: Tired of waiting for RTL?  TL-Verilog's smaller models come to life faster.

 

Fewer bugs: Redwoods are resistant to bugs!  Sandpipers eat them!  Numerous studies as well as the engineer's gospel "The Mythical Man-Month" conclude that complexity and bug count grow more than proportionally to code size.  You want your logic designers using SandPiper.

 

Less Churn: Do you feel like you spend your life chasing unstable RTL?  Get out of that funk!  Bugs are introduced constantly by changes made for physical implementation reasons, the most common of which is retiming logic to meet cycle time.  This activity is a factory for bugs in RTL, but it is much easier and safer with TL-Verilog.  The RTL will be more stable and your logic designers will have more time to focus on the functional changes you need.  Additionally, the introduction of clock gating logic, which creates bugs late in the design process, is all but eliminated with TL-Verilog and SandPiper.  You want your logic designers using SandPiper.

 

Debug: You can use your existing debug tools with RTL produced by SandPiper.  The produced RTL is, in fact, easier to debug than hand-written code because it follows a predictable structure and a consistent signal naming methodology no matter who wrote the source code.  About half of the produced RTL is correct-by-construction.  This includes signal declarations, state elements (flip-flops and latches), and clock-gating logic.  This code is placed in separate files that you know you can ignore.  The remaining code is directly translated from the source code and adheres to a strict signal naming convention.  If two signal names differ only by stage number, two cycles of delay is exactly the difference, no question.  You want your logic designers using SandPiper.